XCENA MX1 CXL Computational Memory Shares a KV Cache Across Inference Servers and Powers SK hynix CXL Hybrid Memory at OCP 2026
XCENA showed two AI inference demonstrations built on its MX1 CXL computational memory at the OCP Global Summit 2026 in San Jose: a KV cache shared across inference servers through a CXL memory pool, and vector search for retrieval-augmented generation (RAG) run inside the memory device. SK hynix also unveiled a CXL Hybrid Memory product The post XCENA MX1 CXL Computational Memory Shares a KV C…
XCENA's OCP 2026 demos show CXL memory pooling moving past capacity expansion toward active roles in AI inference: one setup shares a KV cache across multiple inference servers, while another runs RAG vector search inside the memory device itself. SK hynix's CXL Hybrid Memory unveil at the same event adds a major DRAM vendor to the CXL tier. For buyers, this signals that memory architecture decisions for inference clusters may soon extend beyond DIMM count and speed to include pooled, shared tiers. These are demonstrations rather than shipping deployments, so near-term planning still centers on DDR5 RDIMM, MRDIMM, and HBM supply; if you're sizing a refresh, check live inventory or send us an RFQ to see what's available today.